Neuromorphic X1

Neuromorphic X1

Overview

Neuromorphic X1 is a compact and efficient analog in-memory compute macro designed for next-generation edge AI applications. Built on a 32×32 1T1R crossbar array, it leverages analog weights to perform multiply-accumulate operations directly in memory, minimizing data movement and maximizing energy efficiency.

With integrated decoders and sense amplifiers, the X1 macro delivers 1kb of analog weight storage in a compact 0.28 mm² area. Its Wishbone bus compatibility ensures seamless integration into digital SoCs, including Caravel-based platforms.

Key Features

  • In-Memory Compute: Efficient analog MACs for AI workloads
  • Compact Footprint: 0.28 mm² including peripheral circuitry
  • Wishbone Interface: Easy integration with standard digital buses
  • Ready for Tapeout: Fully synthesized and foundry-compatible

Neuromorphic X1 enables AI processing at the edge with ultra-low power and area, making it ideal for sensor-rich, power-constrained environments.

Memory Features

  • Synchronous Read / Write cycles (single-clock timing)
  • Active-high bit enables for per-lane writes
  • Single R/W control — 0 = Write, 1 = Read / Compute
  • Bit-level (1 T 1 R) programming & verify for precise analog weights
  • Separate DI / DO pins to support simultaneous sense & program operations
  • Split power rails — core array vs. digital periphery
  • Body-bias pins for leakage control and conductance trimming
  • Full scan-chain test mode covering address, data & control logic
  • Wafer-level burn-in test mode for early-life reliability screening
  • Global word-line-OFF option (all WLs clamped when inactive)
  • Macro power-switch hooks for deep-sleep isolation
  • Clock-gating throughout periphery to minimize dynamic power during idle

Block Diagram

Block Diagram

Pin Description

Name Type Direction Description
CLKin CMOS IN Clock synchronizes the operations of the memory. All inputs are sampled on rising edge of clock.
RSTin CMOS IN This is the reset pin, which is active high. Reset is applied when this pin is high, and deasserted when the pin is low.
EN CMOS IN EN (Chip Enable) is high (and TM low), read and write operation is performed.
R_WB CMOS IN This is the read/write control and sampled on rising edge of clock. When R_WB is high, the memory is in a read cycle mode. When R_WB is low, the memory is in write cycle mode.
AD[31:0] CMOS IN This is the address input pin. When the value on this pin is 32'h3000_0004, the read or write operation starts; otherwise, no action is taken.
DI[31:0] CMOS IN This is the data input bus. Data is written into the memory location specified
BEN[31:0] CMOS IN Each bit of the BEN bus selects one bit of the DI bus. When one or more BEN inputs are high (active), and R_WB is low (write enabled) then the selected bits will be written into the memory.
TM IN IN When TM (Testmode)is high, memory is in testmode and normal memory operation is disabled. Inputs are tied to outputs through scan chain logic.
SM CMOS IN When SM (Scan chain control) is high, output of a input register is passed to next register. When low, input register receives input from input pin.
ScanInCC CMOS IN Input to Address and Control scan chain.
ScanInDL CMOS IN Input to Data scan chain (left side of the macro).
ScanInDR CMOS IN Input to Data scan chain (right side of the macro).
DO[31:0] CMOS OUT Data from the memory location selected by address is driven onto DO during a read cycle. In a write cycle, data to be written is driven onto DO. If there is no read or write, while memory is enabled, DO will hold previous data.
ScanOutCC CMOS IN Output of Scan Chain of address and control pins. Note - DO is output of scan chain of data input pins.

Specifications

DC Specifications

Conditions
  • Process Condition : Typical
  • Junction Temperature : 25.000 deg C
  • Operating Voltage : 1.800 V
  • Operating Frequency : 100 MHz
Power Dissipation When R_WB=HIGH
  • READ Active = 77.566 pJ
  • READ Active = 8.618 mA
  • READ Peak = 80.613 mA
Power Dissipation When R_WB=LOW
  • WRITE Active = 69.948 pJ
  • WRITE Active = 7.772 mA
  • WRITE Peak = 79.072 mA
Power Dissipation When EN=LOW, All Other Inputs Switching
  • Standby = 0.174 pJ
  • Standby = 0.019 mA
  • Standby Peak = 0.470 mA
Power Dissipation When TM=HIGH, Clock Switching
  • Test Mode = 9.603 pJ
  • Test Mode = 1.067 mA
  • Test Peak = 33.687 mA
Leakage: Power switches ON, Disabled (EN=LOW)
  • Power = 41611.200 pW
  • Current = 23.120 nA
Leakage - One or More Power switches OFF (VPWRPC=HIGH or VPWRAC=HIGH)
  • Power = 1420.430 pW
  • Current = 0.790 nA

AC Specifications

Conditions
  • Process Condition : Typical
  • Junction Temperature : 25.000 deg C
  • Operating Voltage : 1.800 V
  • Operating Frequency : 100 MHz

Timing Diagram

Waveform